1. The Field of the Invention
This invention relates to the field of printed feature manufacturing, such as integrated circuit manufacturing. In particular, this invention relates to computing corrections using a proximity effects model at evaluation points to achieve improved agreement between a design layout and an actual printed feature.
2. Description of Related Art
To fabricate an integrated circuit (IC), engineers first use a logical electronic design automation (EDA) tool, also called a functional EDA tool, to create a schematic design, such as a schematic circuit design consisting of symbols representing individual devices coupled together to perform a certain function or set of functions. Such tools are available from CADENCE DESIGN SYSTEMS and from SYNOPSYS. The schematic design must be translated into a representation of the actual physical arrangement of materials upon completion, called a design layout. The design layout uses a physical EDA tool, such as those available from CADENCE and AVANT!. If materials must be arranged in multiple layers, as is typical for an IC, the design layout includes several design layers.
After the arrangement of materials by layer is designed, a fabrication process is used to actually form material on each layer. That process includes a photo-lithographic process using a mask having opaque and transparent regions that causes light to fall on photosensitive material in a desired pattern. After light is shined through the mask onto the photosensitive material, the light-sensitive material is subjected to a developing process to remove those portions exposed to light (or, alternatively, remove those portions not exposed to light). Etching, deposition, diffusion, or some other material altering process is then performed on the patterned layer until a particular material is formed with the desired pattern in the particular layer. The result of the process is some arrangement of material in each of one or more layers, here called printed features layers.
Because of the characteristics of light in photolithographic equipment, and because of the properties of the material altering processes employed, the pattern of transparent and opaque areas on the mask is not the same as the pattern of materials on the printed layer. A mask design process is used, therefore, after the physical EDA process and before the fabrication process, to generate one or more mask layouts that differ from the design layers. When formed into one or more masks and used in a set of photolithographic processes and material altering processes, these mask layouts produce a printed features layer as close as possible to the design layer.
The particular size of a feature that a design calls for is the feature's critical dimension. The resolution for the fabrication process corresponds to the minimum sized feature that the photolithographic process and the material processes can repeatably form on a substrate, such as a silicon wafer. As the critical dimensions of the features on the design layers become smaller and approach the resolution of the fabrication process, the consistency between the mask and the printed features layer is significantly reduced. Specifically, it is observed that differences in the pattern of printed features from the mask depend upon the size and shape of the features on the mask and the proximity of the features to one another on the mask. Such differences are called proximity effects.
Some causes of proximity effects are optical proximity effects, such as diffraction of light through the apertures of the optical systems and the patterns of circuits that resemble optical gratings. Optical proximity effects also include underexposure of concave corners (inside corners with interior angles greater than 180 degrees) and overexposure of convex corners (outside corners with interior angles less than 180 degrees), where the polygon represents opaque regions, and different exposures of small features compared to large features projected from the same mask. Other causes of proximity effects are non-optical proximity effects, such as sensitivity of feature size and shape to angle of attack from etching plasmas or deposition by sputtering during the material altering processes, which cause features to have shapes and sizes that have decayed from or accumulated onto their designed shapes and sizes.
In attempts to compensate for proximity effects, the mask layouts can be modified. A proximity effects model is often developed and used to predict the location of edges in the printed layer, given a mask layout.
A proximity effects model is typically built for a particular suite of equipment and equipment settings assembled to perform the fabrication process. The model is often built by performing the fabrication process one or a few times with test patterns on one or more mask layouts, observing the actual features printed (for example with a scanning electron micrograph), and fitting a set of equations or matrix transformations that most nearly reproduce the locations of edges of features actually printed as output when the test pattern is provided as input. The output of the proximity effects model is often expressed as an optical intensity. Other proximity effects models provide a calibrated output that includes a variable intensity threshold as well as optical intensity. Some proximity effects models provide a calibrated output that indicates a printed edge location relative to an intensity threshold value as a spatial deviation. Thus, some model outputs can take on one or more values that vary practically continuously between some minimum value and some maximum value.
Once a proximity effects model is produced, it can be used in the fabrication design process. For example, the proximity effects model is run with a proposed mask layout to produce a predicted printed features layer. The predicted printed features layer is compared to the design layer and the differences are analyzed. Based on the differences, modifications to the proposed mask layout are made.
In conventional systems, the distances between the predicted edges and the edges of the items on the design layout are used to correct the mask. For example, as shown in FIG. 1, the proximity model predicts that an original edge in the mask 110 aligned with a corresponding edge in the design layer, will result in a printed edge 120. The predicted printed edge 120 is displaced X units inward from the edge 110 as indicated by vector 132. For simplicity of illustration, the positions of the predicted printed features are shown on the same scale as the items in the design and fabrication layouts, both original and adjusted. The distance X units is measured on the common scale. The conventional system in this example modifies the mask layout by moving a segment corresponding to this edge 110 in the original mask layout outward, in the opposite direction, by a correction distance C equal to X distance units, as indicated by vector 134. The new edge in the adjusted mask is denoted by segment 114. In other conventional systems, not shown, the correction vector C has a magnitude given by a constant proportion of X.
FIG. 1 also shows that the difference between the predicted edge 120 and the original fabrication layout edge 110 is computed from an evaluation point 105 on a segment 112 of the edge 110. The segment 112 in the original fabrication layout is bounded by dissection points 102 and 104. The correction computed for the evaluation point 105, indicated by vector 134, is then applied to the whole segment 112, resulting in a new edge 114 for the adjusted mask layout. At least because of this change, the adjusted mask layout with edge 114 differs from the original fabrication layout with edge 110. The vertices 142 and 144 of the new edge 114 in the adjusted fabrication layout still correspond to the dissection points 102 and 104 on the original fabrication layout edge. After making these corrections to all segments in the proposed, original mask layout, a final, adjusted mask layout is generated that is used to form a mask used in the fabrication process.
A problem with the conventional technique is that changes in a printed features layer, such as a layer on a silicon wafer, may not be equivalent or linearly related to changes in position of an edge in a fabrication layout, such as a mask layout. As a consequence, a change in mask edge by X units, or proportional to X units, in general does not produce a movement of the printed feature edge 120 by X units, even when mapped at the same scale. The relationship between changes in the mask and changes in the printed features is often referred to as the Mask Error Factor (MEF) or the Mask Error Enhancement Function (MEEF). For integrated circuited, the MEEF is often computed as the partial derivative of the wafer dimension with respect to the mask dimension on the common scale.
The deviation of the MEEF from a constant value often prevents a mask corrected in the conventional way from fabricating printed features that meet the spatial tolerance required by a manufacturing specification, i.e., the spec tolerance.
In this field, therefore, new ways are needed to compute corrections at evaluation points, that account for non-equivalence and non-linearity in the MEEF, so that the printed edges are guaranteed to lie within a spec tolerance of the design layer whenever such is possible for a given suite of fabrication equipment.